1、外文文献翻译DS18B20 Digital ThermometerDESCRIPTIONThe DS18B20 Digital Thermometer provides 9 to 12-bit (configurable) temperature readings which indicate the temperature of the device.Information is sent to/from the DS18B20 over a 1-Wire interface, so that only one wire (and ground) needs to be connected
2、from a central microprocessor to a DS18B20. Power for reading, writing, and performing temperature conversions can be derived from the data line itself with no need for an external power source.Because each DS18B20 contains a unique silicon serial number, multiple DS18B20s can exist on the same 1-Wi
3、re bus. This allows for placing temperature sensors in many different places. Applications where this feature is useful include HVAC environmental controls, sensing temperatures inside buildings, equipment or machinery, and process monitoring and control.FEATURESUnique 1-Wire interface requires only
4、 one port pin for communicationMultidrop capability simplifies distributed temperature sensing applicationsRequires no external componentsCan be powered from data line. Power supply range is 3.0V to 5.5VZero standby power requiredMeasures temperatures from -55C to+125C. Fahrenheit equivalent is -67F
5、 to +257FThermometer resolution is programmable from 9 to 12 bitsConverts 12-bit temperature to digital word in 750 ms (max.)User-definable, nonvolatile temperature alarm settingsAlarm search command identifies and addresses devices whose temperature is outside of programmed limits (temperature alar
6、m condition)Applications include thermostatic controls, industrial systems, consumer products,thermometers, or any thermally sensitivesystem.PIN ASSIGNMENTPIN DESCRIPTIONGND - GroundDQ - Data In/OutVDD - Power Supply VoltageNC - No ConnectDETAILED PIN DESCRIPTION OVERVIEWThe block diagram of Figure
7、1 shows the major components of the DS18B20. The DS18B20 has four main data components: 1) 64-bit lasered ROM, 2) temperature sensor, 3) nonvolatile temperature alarm triggers TH and TL. The device derives its power from the 1-Wire communication line by storing energy on an internal capacitor during
8、 periods of time when the signal line is high and continues to operate off this power source during the low times of the 1-Wire line until it returns high to replenish the parasite (capacitor) supply. As an alternative, the DS18B20 may also be powered from an external 3 volt - 5.5 volt supply.DS18B2
9、0 BLOCK DIAGRAM Figure 1Communication to the DS18B20 is via a 1-Wire port. With the 1-Wire port, the memory and control functions will not be available before the ROM function protocol has been established. The master must first provide one of five ROM function commands: 1) Read ROM, 2) Match ROM, 3
10、) Search ROM, 4) Skip ROM, or 5) Alarm Search. These commands operate on the 64-bit lasered ROM portion of eachdevice and can single out a specific device if many are present on the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. After a ROM function
11、 sequence has been successfully executed, the memory and control functions are accessible and the master may then provide any one of the six memory and control function commands. One control function command instructs the DS18B20 to perform a temperature measurement. The result of this measurement w
12、ill be placed in the DS18B20s scratch-pad memory, and may be read by issuing a memory function command which reads the contents of the scratchpad memory. The temperature alarm triggers TH and TL consist of 1 byte EEPROM each. If the alarm search command is not applied to the DS18B20, these registers
13、 may be used as general purpose user memory. The scratchpad also contains a configuration byte to set the desired resolution of the temperature to digital conversion. Writing TH, TL, and the configuration byte is done using a memory function command. Read access to these registers is through the scr
14、atchpad. All data is read and written least significant bit first.1-WIRE BUS SYSTEMThe 1-Wire bus is a system which has a single bus master and one or more slaves. The DS18B20 behaves as a slave. The discussion of this bus system is broken down into three topics: hardware configuration, transaction
15、sequence, and 1-Wire signaling (signal types and timing).HARDWARE CONFIGURATIONThe 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain
16、 or 3-state outputs. The 1-Wire port of the DS18B20 (DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus requires a pullup resistor of approximately 5 k.The idle state for the 1-Wi
17、re bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire bus is in the inactive (high) state during the recovery period. If this does not occur an
18、d the bus is left low for more than 480 s, all components on the bus will be reset.HARDWARE CONFIGURATION TRANSACTION SEQUENCEThe protocol for accessing the DS18B20 via the 1-Wire port is as follows:_ Initialization_ ROM Function Command_ Memory Function Command_ Transaction/DataINITIALIZATIONAll tr
19、ansactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS18B20 is on the bus and is ready t
20、o operate. For more details, see the “1-Wire Signaling” section.ROM FUNCTION COMMANDSOnce the bus master has detected a presence, it can issue one of the five ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 5)Read ROM 3
21、3hThis command allows the bus master to read the DS18B20s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS18B20 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at
22、 the same time (open drain will produce a wired AND result).Match ROM 55hThe match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS18B20 on a multidrop bus. Only the DS18B20 that exactly matches the 64-bit ROM sequence will respond to the following memor
23、y function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus.Skip ROM CChThis command can save time in a single drop bus system by allowing the bus master to access the memory functions wit
24、hout providing the 64-bit ROM code. If more than one slave is present on the bus and a Read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired AND result).Search ROM F0hWhen a sy
25、stem is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus.Alarm Search EChThe flowchart o
26、f this command is identical to the Search ROM command. However, the DS18B20 will respond to this command only if an alarm condition has been encountered at the last temperature measurement. An alarm condition is defined as a temperature higher than TH or lower than TL. The alarm condition remains se
27、t as long as the DS18B20 is powered up, or until another temperature measurement reveals a non-alarming value. For alarming, the trigger values stored in EEPROM are taken into account. If an alarm condition exists and the TH or TL settings are changed, another temperature conversion should be done t
28、o validate any alarm conditions.Example of a ROM SearchThe ROM search process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After
29、one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes.The following example of the ROM search process assumes four different devices are connected to the same 1-Wire bus. The ROM data
30、of the four devices is as shown:ROM1 00110101.ROM2 10101010.ROM3 11110101.ROM4 00010001.The search process is as follows:1. The bus master begins the initialization sequence by issuing a reset pulse. The slave devices respond by issuing simultaneous presence pulses.2. The bus master will then issue
31、the Search ROM command on the 1-Wire bus.3. The bus master reads a bit from the 1-Wire bus. Each device will respond by placing the value of the first bit of their respective ROM data onto the 1-Wire bus. ROM1 and ROM4 will place a 0 onto the 1-Wire bus, i.e., pull it low. ROM2 and ROM3 will place a
32、 1 onto the 1-Wire bus by allowing the line to stay high. The result is the logical AND of all devices on the line, therefore the bus master sees a 0. The bus master reads another bit. Since the Search ROM data command is being executed,all of the devices on the 1-Wire bus respond to this second rea
33、d by placing the complement of the first bit of their respective ROM data onto the 1-Wire bus. ROM1 and ROM4 will place a 1 onto the 1-Wire, allowing the line to stay high. ROM2 and ROM3 will place a 0 onto the 1-Wire, thus it will be pulled low. The bus master again observes a 0 for the complement
34、of the first ROM data bit. The bus master has determined that there are some devices on the 1-Wire bus that have a 0 in the first position and others that have a 1. The data obtained from the two reads of the three-step routine have the following interpretations:4. The bus master writes a 0. This de
35、selects ROM2 and ROM3 for the remainder of this search pass,leaving only ROM1 and ROM4 connected to the 1-Wire bus.5. The bus master performs two more reads and receives a 0-bit followed by a 1-bit. This indicates that all devices still coupled to the bus have 0s as their second ROM data bit.6. The
36、bus master then writes a 0 to keep both ROM1 and ROM4 coupled.7. The bus master executes two reads and receives two 0-bits. This indicates that both 1-bits and 0-bits exist as the 3rd bit of the ROM data of the attached devices.8. The bus master writes a 0-bit. This deselects ROM1, leaving ROM4 as t
37、he only device stillconnected.9. The bus master reads the remainder of the ROM bits for ROM4 and continues to access the part ifdesired. This completes the first pass and uniquely identifies one part on the 1-Wire bus.10. The bus master starts a new ROM search sequence by repeating steps 1 through 7
38、.11. The bus master writes a 1-bit. This decouples ROM4, leaving only ROM1 still coupled.12. The bus master reads the remainder of the ROM bits for ROM1 and communicates to the underlying logic if desired. This completes the second ROM search pass, in which another of the ROMs was found.13. The bus
39、master starts a new ROM search by repeating steps 1 through 3.NOTE:The bus master learns the unique ID number (ROM data pattern) of one 1-Wire device on each ROMSearch operation. The time required to derive the parts unique ROM code is:960 s + (8 + 3 x 64) 61 s = 13.16 msThe bus master is therefore
40、capable of identifying 75 different 1-Wire devices per second. Single chip brief introduction:The monolithic integrated circuit said that the monolithic micro controller, it is not completes some logical function the chip, but integrates a computer system to a chip on. Summary speaking: A chip has b
41、ecome a computer. Its volume is small, the quality is light, and the price cheap, for the study, the application and the development has provided the convenient condition. At the same time, the study use monolithic integrated circuit is understands the computer principle and the structure best choic
42、e.The monolithic integrated circuit interior also uses with the computer function similar module, for instance CPU, memory, parallel main line, but also has with the hard disk behave identically the memory component7 what is different is its these part performance is opposite our home-use computer w
43、eak many, but the price is also low, generally does not surpass 10 Yuan then Made some control electric appliance one kind with it is not the very complex work foot, We use now the completely automatic drum washer, the platoon petti-coat pipe: VCD and so on Inside the electrical appliances may see i
44、ts form! It is mainly takes the control section the core part.It is one kind of online -like real-time control computer, online -like is the scene control, needs to have the strong antijamming ability, the low cost, this is also and the off-line type computer (for instance home use PC,) main differe
45、nce The monolithic integrated circuit is depending on the procedure, and may revise. Realizes the different function through the different procedure, particularly special unique some functions, this is other component needs to take the very big effort to be able to achieve, some are the flowered big
46、 strength is also very difficult to achieve. One is not the very complex function, if develops in the 50s with the US 74 series, or the 60ss CD4000 series these pure hardware do decides, the electric circuit certainly arc a big PCB board ! But if, if succeeded in the 70s with the US puts in the mark
47、et the series monolithic integrated circuit, the result will have the huge difference. Because only the monolithic integrated circuit compiles through you the procedure may realize the high intelligence, high efficiency, as well as redundant reliability The CPU is the key component of a digital comp
48、uter. Its purpose is to decode instruction received from memory and perform transfers, arithmetic, logic, and control operations with data stored in internal registers, memory, or I/O interface units. Externally, the CPU provides one or more buses for transferring instructions, data, and control inf
49、ormation to and from components connected to it. A microcontroller is present in the keyboard and in the monitor in the generic computer; thus these components are also shaded. In such microcontrollers, the CPU may be quite different from those discussed in this chapter. The word lengths may be short, the number of registers small, and the instruction sets limited. P
陕公网安备 61072602000132号 违法和不良信息举报：0916-4228922